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w989 d 6db / w989d2db 512 m b m obile lp s dr publication release date: mar. 1 9 , 2014 - 1 - revision: a01 - 001 table of contents - 1. general description ................................ ................................ ................................ ......... 4 2. features ................................ ................................ ................................ ................................ . 4 3. order information ................................ ................................ ................................ ............. 4 4. ball configuration ................................ ................................ ................................ ............ 5 4.1 ball assignment: lpsdr x16 ................................ ................................ ......................... 5 4.2 ball assignment: lpsdr x32 ................................ ................................ ......................... 6 5. ball description ................................ ................................ ................................ .................. 7 5.1 signal description ................................ ................................ ................................ ........... 7 5.2 addressing table ................................ ................................ ................................ ............ 8 6. block diagram ................................ ................................ ................................ ...................... 9 7. functional descripti on ................................ ................................ ................................ .. 10 7.1 command function ................................ ................................ ................................ ...... 10 7.1.1 table 1. truth table (note (1) and (2)) ................................ ................................ ... 10 7.1.2 functional truth table (see note 1) ................................ ................................ ...... 11 7.1.3 functional truth table for cke ................................ ................................ .............. 14 7.1.4 bank activ ate command ................................ ................................ ........................ 15 7.1.5 bank precharge command ................................ ................................ .................... 15 7.1.6 precharge all command ................................ ................................ ........................ 15 7.1. 7 write command ................................ ................................ ................................ ...... 15 7.1.8 write with auto precharge command ................................ ................................ .... 15 7.1.9 read command ................................ ................................ ................................ ..... 15 7.1.10 read with auto precharge command ................................ ................................ .... 15 7.1.11 extended mode register set command ................................ ................................ 16 7.1.12 mode register set command ................................ ................................ ................ 16 7.1.13 no - operation command ................................ ................................ ........................ 16 7.1.14 burst stop command ................................ ................................ ............................. 16 7.1.15 device deselect command ................................ ................................ .................... 16 7.1.16 auto refresh command ................................ ................................ ......................... 16 7.1.17 self refresh entry command ................................ ................................ ................. 16 7.1.18 self refresh exit command ................................ ................................ ................... 17 7.1.19 clock suspend mode entry/power down mode entry command .......................... 17 7.1.20 clock suspend mode exit/power down mode exit command ............................... 17 7.1.21 data write/output enable, data mask/output disable command .......................... 17 8. operation ................................ ................................ ................................ ............................. 17 8.1 read operation ................................ ................................ ................................ ............. 17
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 2 - revision: a01 - 001 8.2 write operation ................................ ................................ ................................ ............. 18 8.3 precharg e ................................ ................................ ................................ ..................... 18 8.3.1 auto precharge ................................ ................................ ................................ ....... 18 8.3.2 read with auto precharge interrupted by a read (with or without auto precharge) 19 8.3.3 read with auto precharge interrupted by a write (with or without auto precharge) 19 8.3.4 write with auto precharge interrupted by a read (with or without auto precharge) 20 8.3.5 write with auto precharge interrupted by a write (with or without auto precharge) 20 8.4 burst termination ................................ ................................ ................................ .......... 21 8.5 mode register operation ................................ ................................ .............................. 22 8.5.1 burst length field (a2~a0) ................................ ................................ ..................... 22 8.5.2 addressing mode select (a3) ................................ ................................ ................. 22 8.5.3 addressing sequence for sequential mode ................................ ............................ 22 8.5.4 addressing sequence fo r interleave mode ................................ ............................. 23 8.5.5 addressing sequence example (burst length = 8 and input address is 13) ......... 23 8.5.6 read cycle cas latency = 3 ................................ ................................ ................. 23 8.5.7 cas latency field (a6~a4) ................................ ................................ ..................... 24 8.5.8 mode register definition ................................ ................................ ........................ 24 8.6 extended mode register description ................................ ................................ ........... 25 8.7 simplified state diagram ................................ ................................ .............................. 26 9. electrical character istics ................................ ................................ ......................... 27 9.1 absolute maximum ratings ................................ ................................ .......................... 27 9.2 operating conditions ................................ ................................ ................................ .... 27 9.3 capacitance ................................ ................................ ................................ .................. 27 9.4 dc characteristics ................................ ................................ ................................ ........ 28 9.5 automatic temperature compensated self refresh current feature ......................... 28 9.6 ac characteristics and operating condition ................................ ................................ 29 9.6.1 ac characteristics ................................ ................................ ................................ .. 29 9.6.2 ac test condition ................................ ................................ ................................ .. 30 9.6.3 ac latency characteristics ................................ ................................ .................... 31 10. control timing wavef orms ................................ ................................ .......................... 32 10.1 command input timing ................................ ................................ ................................ 32 10.2 r ead timing ................................ ................................ ................................ .................. 33 10.3 control timing of input data (x16) ................................ ................................ ................ 34 10.4 control timing of output data (x16) ................................ ................................ ............. 35 10.5 control timing of input data (x32) ................................ ................................ ................ 36 10.6 control timing of output data (x32) ................................ ................................ ............. 37 10.7 mode register set (mrs) cycle ................................ ................................ ................... 38
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 3 - revision: a01 - 001 10.8 extended mode register set (emrs) cycle ................................ ................................ . 39 11. operating timing exa mple ................................ ................................ ............................. 40 11.1 interleaved bank read (burst length = 4, cas latency = 3) ................................ ...... 40 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto - precharge) ........... 41 11.3 interleaved bank read (burst length = 8, cas latency = 3) ................................ ...... 42 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto - precharge) ........... 43 11.5 interleaved bank write (burst length = 8) ................................ ................................ ... 44 11.6 interleaved bank write (burst l ength = 8, auto - precharge) ................................ ........ 45 11.7 page mode read (burst length = 4, cas latency = 3) ................................ ............... 46 11.8 page mode read / write (burst length = 8, cas latency = 3) ................................ ... 47 11.9 auto - precharge read (burst length = 4, cas latency = 3) ................................ ........ 48 11.10 auto - precharge write (burst le ngth = 4) ................................ ................................ .... 49 11.11 auto refresh cycle ................................ ................................ ................................ ..... 50 11.12 self refresh cycle ................................ ................................ ................................ ....... 51 11.13 burst read and single write (burst length = 4, cas latency = 3) ............................ 52 11.14 power down mode ................................ ................................ ................................ ...... 53 11.15 deep power down mode entry ................................ ................................ ................... 54 11.16 deep power down mode exit ................................ ................................ ..................... 55 11.17 auto - precharge timing (read cycle) ................................ ................................ .......... 56 11.18 auto - precharge timing (write cycle) ................................ ................................ .......... 57 11.19 timing chart of read to write cycle ................................ ................................ ........... 58 11.20 timing chart of write to read cycle ................................ ................................ ........... 58 11.21 timing chart of burst stop cycle (burst stop command) ................................ .......... 59 11.22 timing chart of burst stop cycle ( precharge command) ................................ .......... 59 11.23 cke/dqm input timing (write cycle) ................................ ................................ ......... 60 11.24 cke/dqm input timing (read cycle) ................................ ................................ ......... 61 12. package specificatio n ................................ ................................ ................................ .... 62 12.1 lpsdr x16 ................................ ................................ ................................ ................... 62 12.2 lpsdr x32 ................................ ................................ ................................ ................... 63 13. revision history ................................ ................................ ................................ ................ 64
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 4 - revision: a01 - 001 1. general description the winbond 512mb low power sdram is a low power synchronous memory containing 536,870,912 memory cells fabricated with winbond high performance process technology. it is designed to consum e less power than the ordinary sdram with low power features essential for applications which use batteries. it is available in two organizations: 4,194,304 - words 4 banks 32 bits or 8,388,608 words 4 banks 16 bits. the devic e operates in a fully synchronous mode, and the output data are synchronized to positive edges of the system clock and is capable of delivering data at clock rate up to 1 66 m hz . the device supports special low power functions such as partial array self refr esh (pasr) and automatic temperature co mpensated self refresh (atcsr). the low p ower sdram is suitable for 2.5g / 3g cellular phone, pda, digital still camera, mobile game consoles and other handheld applications where large memory density and low power co nsumption are required. the device operates from 1.8v power supply, and supports the 1.8v lvcmos bus interface . 2. features ? power supply v dd = 1. 7 v~1.9 5 v ? v dd q = 1. 7 v~1.9 5 v ? frequency : 166mhz( - 6) ? standard self refresh mode ? programmable partial array self refresh ? power down mode ? deep power down mode (dpd) ? programmable output buffer driver strength ? automatic temperature compensated self refresh ? cas latency: 2 and 3 ? burst length: 1, 2, 4 , 8 , and full page ? refresh: refresh cycle 64m s ? interface: lvcmos ? support package: 54 balls vfbga (x16) 90 balls vfbga (x32) ? operating temperature range : extended ( - 25 c ~ + 85 c ) industrial ( - 40 c ~ + 85 c ) 3. order information part number vdd/vddq i/o width package others W989D6DBgx6i 1.8v/1.8v 16 54 balls vfbga 166mhz, - 40 c ~85 c W989D6DBgx6e 1.8v/1.8v 16 54 balls vfbga 166mhz, - 25 c ~85 c w989d2dbjx6i 1.8v/1.8v 32 90 balls vfbga 166mhz, - 40 c ~85 c w989d2dbjx6e 1.8v/1.8v 32 90 balls vfbga 166mhz, - 25 c ~85 c
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 5 - revision: a01 - 001 4. ball configuration 4.1 ball assignment: lpsdr x 16 a 5 a 7 a 9 d q 0 a 1 2 v s s a 4 a 8 a 1 1 a 2 a 3 b a 0 / c s c k e v d d a 1 b a 1 / c a s 1 2 6 5 7 9 8 4 3 c b a g d e h f j v d d q v s s q d q 3 d q 5 / w e d q 1 3 d q 8 d q 1 2 d q 1 0 v d d q d q 2 d q 7 v d d v s s a 1 0 a 0 a 6 / r a s v d d d q 1 d q 4 v d d q d q 6 v s s q l d q m v s s q u d q m c l k v s s d q 1 5 d q 1 4 d q 1 1 v s s q d q 9 v d d q n c t o p v i e w
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 6 - revision: a01 - 001 4.2 ball assignment: lpsdr x32 c k e a 8 a 6 d q 2 3 a 4 c l k a 9 a 7 a 5 / w e / c a s / c s b a 0 a 1 0 a 1 a 3 d q m 0 / r a s b a 1 a 0 a 2 1 2 6 5 7 9 8 4 3 c b a p n g d e m h l f k r j v d d v d d v d d v d d q v d d q v d d q v d d q v d d q v d d v d d q v d d q v d d q v d d q v s s q v s s q v s s q v s s q v s s q v s s q v s s q v s s q v s s q v s s q v d d q n c n c a 1 1 n c a 1 2 d q m 2 d q 2 1 d q 1 9 d q 2 0 d q 2 2 d q 1 8 d q 1 7 d q 1 6 d q 7 d q 6 d q 5 d q 1 d q 3 d q 4 d q 0 d q 2 v s s v s s v s s v s s d q m 3 d q m 1 d q 2 6 d q 2 4 d q 2 8 d q 2 7 d q 2 5 d q 2 9 d q 3 0 d q 3 1 d q 1 5 d q 1 3 d q 1 1 d q 1 2 d q 1 4 d q 1 0 d q 9 d q 8 n c n c t o p v i e w
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 7 - revision: a01 - 001 5. ball description 5.1 signal description ball name function description a [n:0] address multiplexed pins for row and column address. a10 is auto precharge select ba0, ba1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. dq0~dq15 (16) dq0~dq31 (32) data input/ output multiplexed pins for data output and input. chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. row address strobe command input. when sampled at the rising edge of the clock, , and defin e the operation to be executed. column address strobe referred to write enable referred to udqm / ldqm(x16) dqm0 ~dqm3 (x32) i/o mask the output buffer is placed at hi - z (with latency of 2 in cl=2, 3;) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency clk clock inputs system clock used to sample inputs on the rising edge of clock. cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode or self refresh mode is entered. v dd power power supply for input buffers and logic circuit inside dram. vss ground ground for input buffers and logic circuit inside dram. v ddq power for i/o buffer power supply separated from v dd , used for o utput buffers to improve noise. v ssq ground for i/o buffer separated ground from v ss , used for output buffers to improve noise. nc no connection no connection cs ras cas we
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 8 - revision: a01 - 001 5.2 addressing table item 512 mb number of banks 4 bank address pins ba0,ba1 auto precha r ge pin a10 /ap type package x 16 row addresses a0 - a12 column addresses a0 - a 9 x32 row addresses a0 - a1 2 column addresses a0 - a 8
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 9 - revision: a01 - 001 6. block diagram d q 0 d q n d q m c l k c k e a 1 0 c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 2 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 0 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 3 d a t a c o n t r o l c i r c u i t d q b u f f e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 1 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r a 0 a n b a 0 b a 1 c s r a s c a s w e
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 10 - revision: a01 - 001 7. f unctional d escription 7.1 command function 7.1.1 table 1. truth table (note (1) and (2)) symbol c ommand d evice state cken - 1 cken dqm (5) b a 0, 1 a10 a0 - a n act bank activate idle (3) h x x v v v l l h h pre bank precharge any h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto precharge active (3) h x x v h v l h l h mrs mode register set idle h x x v v v l l l l emrs extended mode register set idle h x x v v v l l l l nop no - operation any h x x x x x l h h h bst burst stop active (4) h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto - refresh idle h h x x x x l l l h self self - refresh entry idle h l x x x x l l l h selex self - refresh exit idle (self refresh) l h x x x x h x x x l h h h cse clock suspend mode entry active h l x x x x x x x x pd power down mode entry idle/active (6) h l x x x x h x x x l h h h csex clock suspend mode exit active l h x x x x x x x x pdex power down mode exit any (power down) l h x x x x h x x x l h h x de data write/output enable active h x l x x x x x x x dd data write/output disable active h x h x x x x x x x dpd deep power down mode entry idle h l x x x x l h h l dpde deep power down mode exit idle (dpd) l h x x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input level when commands are provided. cken - 1 signal is the input level one clock cycle before the command is issued. (3) these are state of bank designated by ba0 , ba1 signals. (4) device state is full page burst operation. ( 5 ) x32: dqm0 - 3, x16 : ldqm / udqm ( 6 ) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode. cs ras cas we
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 11 - revision: a01 - 001 7.1.2 functional truth table (see note 1) current state address command action notes idle h x x x x ds l nop l h h x x nop/bs t nop l h l h ba , ca , a1 0 read/read a illeg al 3 l h l l ba , ca, a1 0 w rit/writ a illeg al 3 l l h h ba , r a ac t r o w activating l l h l ba , a1 0 pre/pre a nop l l l h x aref/sel f refresh or sel f r efres h 2 l l l l op - cod e mrs/emr s mod e registe r a c cessin g 2 ro w active h x x x x ds l nop l h h x x nop/bs t nop l h l h ba , ca, a1 0 read/read a begin read: det e rmine a p 4 l h l l ba , ca, a1 0 w rit/writ a begin write: det e rmine a p 4 l l h h ba , r a ac t illega l 3 l l h l ba , a1 0 pre/pre a precharg e 5 l l l h x aref/sel f illeg a l l l l l op - cod e mrs/emr s illegal read h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t burs t stop l h l h ba , ca, a1 0 read/read a term b u rst, n ew read: det e rmin e a p 6 l h l l ba , ca, a1 0 w rit/writ a term b u rst, beg i n write: det e rmi n e a p 6, 7 l l h h ba , r a ac t illega l 3 l l h l ba , a1 0 pre/pre a term b u rst, pre c harging l l l h x aref/sel f illeg a l l l l l op - cod e mrs/emr s illeg a l write h x x x x ds l continue burst t o end. l h h h x no p continue burst t o end l h h l x bs t burst stop, r o w ac tive l h l h ba , ca, a1 0 read/read a term b u rst, star t read: det e rmin e a p 6, 7 l h l l ba , ca, a1 0 w rit/writ a term b u rst, n ew write: det e rmin e a p 6 l l h h ba , r a ac t illega l 3 l l h l ba , a1 0 pre/pre a term b u rst. pre c hargin g 8 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l ras cas we cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 12 - revision: a01 - 001 current state address command action notes read w i t h auto precharge h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t illegal l h l h ba , ca , a1 0 read/read a illegal 3 l h l l ba , ca, a1 0 w rit/writ a illegal 3 l l h h ba , r a ac t illegal 3 l l h l ba , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal write w i th a u to precharge h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t illegal l h l h ba , ca , a1 0 read/read a illegal 3 l h l l ba , ca, a1 0 w rit/writ a illegal 3 l l h h ba , r a ac t illegal 3 l l h l ba , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal precharging h x x x x ds l no p idle af t e r t rp l h h h x no p no p idle af t e r t rp l h h l x bs t illegal l h l h ba , ca , a1 0 read/read a illegal 3 l h l l ba , ca, a1 0 w rit/writ a illegal 3 l l h h ba , r a ac t illegal 3 l l h l ba , a1 0 pre/pre a no p idle af t e r t rp l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal ro w activating h x x x x ds l no p r o w active after t rcd l h h h x no p no p r o w active after t rcd l h h l x bs t illegal l h l h ba , ca , a1 0 read/read a illegal 3 l h l l ba , ca, a1 0 w rit/writ a illegal 3 l l h h ba , r a ac t illegal 3 l l h l ba , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal ras cas we cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 13 - revision: a01 - 001 current state address command action notes write recover i ng h x x x x ds l no p maintai n r o w active afte r t w r l h h h x no p no p maintai n r o w active afte r t w r l h h l x bs t no p maintai n r o w active afte r t w r l h l h ba , ca , a1 0 read/read a begin rea d 7 l h l l ba , ca, a1 0 w rit/writ a begin n e w write l l h h ba , r a ac t illega l 3 l l h l ba , a1 0 pre/pre a illega l 3 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l write recover i ng w i th auto precha r ge h x x x x ds l no p ent e r p rec harge afte r t w r l h h h x no p no p ent e r p rec harge afte r t w r l h h l x bs t no p ent e r p rec harge afte r t w r l h l h ba , ca , a1 0 read/read a illega l 3 l h l l ba , ca, a1 0 w rit/writ a illega l 3 l l h h ba , r a ac t illega l 3 l l h l ba , a1 0 pre/pre a illega l 3 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l refreshing h x x x x ds l no p idle af t e r t rfc l h h h x no p no p idle af t e r t rfc l h h l x bs t no p idle af t e r t rfc l h l x x read/wri t illegal l l h x x act/pre/pre a illegal l l l x x aref/self/ mrs/ emrs illegal mode register accessing h x x x x ds l no p idle af t e r t mrd l h h h x no p no p idle af t e r t mrd l h h l x bs t illega l l h l x x read/wri t illega l l l x x x act/pre/prea/ aref/self/ mrs/ emrs illega l note s : 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle . (cken - 1 = cken = 1) 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address ( ba ), depending on the state of that bank. 4. illegal if t rcd is not satisfied. 5. illegal if t ras is not satisfied. 6. must satisfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which dont satisfy t wr . remark: h = high level, l = low level, x = high or low level (dont care), v = valid data ras cas we cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 1 4 - revision: a01 - 001 7.1.3 functional truth table for cke current state cke address action notes n - 1 n self refresh h x x x x x x n/a l h h x x x x exit self refresh idle after t rfc l h l h h h x exit self refresh idle after t rfc l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain self refresh power - down h x x x x x x n/a l h h x x x x exit power down idle after 1 clock cycle l h h h x l l x x x x x maintain power - down deep power - down h x x x x x x n/a l h x x x x x exit deep power - down exit sequence l l x x x x x maintain deep power - down all banks idle h h x x x x x refer to function truth table h l h x x x x enter power - down 2 h l l h h h x enter power - down 2 h l l h h l x enter deep power - down 3 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal l x x x x x x power - down 2 row active h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h h x enter power down 2 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x power - down row active or maintain pd any state other than listed above h h x x x x x refer to function truth table note s : 1. self refresh can enter only from the all banks idle state. 2. power - down can enter only from the all banks idle or row active state. 3. deep power - down can enter only from the all banks idle state. remark: h = high level, l = low level, x = high or low level (dont care), v = valid data ras cas we cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 15 - revision: a01 - 001 7.1.4 bank activate command ( = l, = h, = h, ba0, ba1 = bank, a0~a n = row address) the bank activate command activates the bank designated by the ba (bank select) signal. row addresses are latched on a0~a n when this command is issued and the cell data is read out to the sense amplifiers. the ma ximum time that each bank can be held in the active state is specified as t ras (max) . 7.1.5 bank precharge command ( = l, = h, = l, ba0, ba1 = bank, a10 = l) the bank precharge command is used to close (or precharge) the bank that is activated. using this command, systems can designated the bank to be closed by specifying the ba address bit setting in the command set. a precharge command can be used to precharg e each bank separately (bank precharge) or all four banks simultaneously (precharge all). after the bank precharge command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state. to re - activate the closed bank, a system has to wait the minimum trp delay after issuing the precharge command before issuing the active command for the device to complete the precharge operation . 7.1.6 precharge all command ( = l, = h, = l , ba0, ba1 = dont care, a10 = h) the precharge all command is used to precharge all banks simultaneously. after this command is issued, all four banks close and transition from the active state to the idle state. 7.1.7 write command ( = h, = l, = l, ba0, ba1 = bank, a10 = l) the write command initiates a write operation to the bank selected by ba0 and ba1 address inputs. the write data is latched at the positive edge of clk. users should preprogram the length of the write data (burst length) and the column access sequence (addressing mode) by setting the mode resister at power - up prior to using the write command. 7.1.8 write with auto precharge command ( = h, = l, = l, ba0, ba1 = bank, a10 = h ) the write with auto precharge command performs the precharge operation automatically after the write operation. the internal precharge starts in the cycles immediately following the cycle in which the last data is written independent of cas latency . 7.1.9 read command ( = h, = l, = h , ba0, ba1 = bank, a10 = l ) the read command performs a read operation to the bank designated by ba 0 - 1 . the read data is issued sequentially synchronized to the positive edges of clk. the length of read data (burst length), addressing mode and cas latency (access time from command in a clock cycle) must be pro grammed in the mode register at power - up prior to the write operation. 7.1.10 read with auto precharge command ( = h, = l, = h , ba0, ba1 = bank, a10 = h ) the read with auto precharge command automatically performs the precharge operation after the read operation. when the cas latency = 3, the internal precharge starts two cycles before the last data is output. when the cas latency = 2, the internal precharg e starts one cycle before the last data is output. ras cas we
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 16 - revision: a01 - 001 7.1.11 extended mode register set command ( = l , = l, = l , ba1, a0~a n = register data) the extended mode register set command is designed to support partial array self refresh, temperature compensated self refresh, and output driver strength/size by allowing users to program each value by setting predefined address bits. the default values in the extend ed mode register after power - up are undefined; therefore this command must be issued during the power - up sequence. also, this command can be issued while all banks are in the idle state. 7.1.12 mode register set command ( = l , = l, = l , ba1, a0~a n = register data) the mode register set command is used to program the values of cas latency, addressing mode and burst length in the mode register. the default values in the mode register after power - up are undefined; therefore this command must be issued during the power - up sequence and re - issued after the deep power down exit command. also, this command can be issued while all banks are in the idle state . 7.1.13 no - operation command ( = h , = h , = h ) the no - operation command is used in cases such as preventing the device from registering unintended commands. the device performs no operation when this command is registered. this command is functionally equivalent to the device deselect command. 7.1.14 burst stop command ( = h , = h , = l ) the burst stop command is used to stop the already activated burst operation. the activated page is left unclosed and future commands can be issued to access the same page of the active bank. if this command is issued during a burst read operation, the read data will go to a hi - z state after a delay equal to the cas latency. if a burst stop command is issued during a burst write operation, then the burst data is terminated and data bus goes to hi - z at the same clock that the burst command is activated. any remaining data from the burst write cycle is ignored. 7.1.15 device deselect command ( = h) the device deselect command disables the command decoder so that the , , and address inputs are ignored. this command is similar to the no - oper ation command. 7.1.16 auto refresh command ( = l , = l, = h , cke = h, ba0, ba1, a0~a n = dont care ) the auto refresh command is used to refresh the row address provided by the internal refresh counter. the refresh operation must be performed 8192 times within 64 m s . the next command can be issued after t rc from the end of the auto refresh command. when the auto refresh command is issued, all banks must be in the idle state. the auto refresh operation is equivalent to the - before - operation in a conventional dram. 7.1.17 self refresh entry command ( = l , = l, = h , cke = l , ba0, ba1, a0~a n = dont care ) when the self refresh entry command is issued, the device enters the self refresh mode. while the device is in self refresh mode, the device automatically refreshes memory cells, and all input and i/o buffers (except the cke buffer) are disabled. by asserting the cke signal high (and by issuing the self refresh exit command), the device exits the self refr esh mode. ras cas we cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 17 - revision: a01 - 001 7.1.18 self refresh exit command (cke = h, = h or cke = h, = h, = h) this command is issued to exit out of the self refresh mode. one t rc delay is required prior to issuing any subsequent command from the end of the self refresh exit command. 7.1.19 clock suspend mode entry/power down mode entry command (cke = l) the internal clk is suspended for one cycle when this command is issued (when cke is asserted low). the device state is held intact while the clk is suspended. on the other hand, when the device is not operating the burst cycle, this command performs entry into power down mode. all input and output buffers (except the cke buffer) are tur ned off in power down mode. 7.1.20 clock suspend mode exit/power down mode exit command (cke = h ) when the internal clk has been suspended, operation of the internal clk is resumed by providing this command (asserting cke high). when the device is in power down mode, the device exits this mode and all disabled buffers are turned on to the active state. any subsequent commands can be issued after one clock cycle from the end of this command. 7.1.21 data write/output enable, data mask/output disable command ( dqm = l/h or ldqm, udqm = l/h or dqm0 - 3=l/h ) during a write cycle, the dqm or ldqm, udqm or dqm0 - 3 signals mask write data. each of these signals control the input buffers per byte. during a read cycle, the dqm or ldqm, udqm or dqm0 - 3 signals control of the output buf fers per byte. i/o org. mask pin masked d q s 16 ldqm dq0~dq7 udqm dq8~dq15 32 dqm0 dq0~dq7 dqm1 dq8~dq15 dqm2 dq16~dq23 dqm3 dq24~dq31 8. operation 8.1 read operation issuing the bank activate command to the idle bank puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized to the positive edges of clk (a burst read operation). the initial read data becomes available after cas latency from the issuing of the read command. the cas latency must be set in the mode register at power - up. in addition, the burst length of read data and addressing mode must be set. each bank is held in the active state unless the precharge command is issued, so that the sense ampl ifiers can be used as secondary cache. when the read with auto precharge command is issued, the precharge operation is performed automatically after the read cycle, then the bank is switched to the idle state. this command cannot be interrupted by any othe r commands. also, when the burst length is 1 and t rcd (min), the timing from the command to the start of the auto precharge operation is shorter than t ras (min). in this case, t ras (min) must be satisfied by extending t rcd . when the precharge operation is performed on a bank during a burst read operation, the burst operation is terminated. when the burst length is full - page, column data is repeatedly read out until the burst stop command or precharge command is issued. ras cas cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 18 - revision: a01 - 001 8.2 writ e operation issuing the write command after t rcd from the bank activate command, the input data is latched sequentially, synchronizing with the positive edges of clk after the write command (burst write operation). the burst length of the write data (burst length) and addressing mode must be set in the mode register at power - up. when the write with auto precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the idle state. this com mand cannot be interrupted by any other command for the entire burst data duration. also, when the burst length is 1 and t rcd (min), the timing from the command to the start of the auto precharge operation is shorter than t ras (min). in this case, t ras (min) must be satisfied by extending t rcd . when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the burst length is full - page, the input data is repeatedly la tched until the burst stop command or the precharge command is issued. when the burst read and single write mode is selected, the write burst length is 1 regardless of the read burst length . 8.3 precharge there are two commands which perform the precharge operation: bank precharge and precharge all. when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank precharge command can precharge one bank independently of the other bank and hol d the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max). therefore, each bank must be precharged within t ras (max) from the bank activate command. the precharge all command can be u sed to precharge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for the active bank and the precharged bank is t hen switched to the idle state. 8.3.1 auto precharge auto precharge is a feature that performs the same individual - bank precharge function described previously, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst , e xcept in the continuous page burst mode where auto precharge does not apply . in the specific case of write burst mode set to single location access with burst length set to continuous, the burst length setting is the overriding setting and auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. another command cannot be issued to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time . winbond sdram supports concurrent auto precharge; cases of concurrent auto precharge for reads and writes are defined below. ras
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 19 - revision: a01 - 001 8.3.2 read with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a read on bank n following the programmed cas latency. the precharge to bank n begins when the read to bank m is registered. 8.3.3 read with auto precharge in terrupted by a write (with or without auto precharge) a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n begins when the write to ba nk m is registered. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p i d l e d o u t a b a n k n , c o l a b a n k m , c o l d t r p - b a n k m p r e c h a r g e t r p - b a n k n r e a d - a p b a n k m r e a d w i t h b u r s t o f 4 i n t e r r u p t b u r s t , p r e c h a r g e r e a d w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e r e a d - a p b a n k n c l = 3 ( b a n k n ) c l = 3 ( b a n k m ) d o n t c a r e n o t e : d q m i s l o w . d o u t a + 1 d o u t d d o u t d + 1 c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p i d l e b a n k n , c o l a b a n k m , c o l d t w r - b a n k m w r i t e - b a c k t r p - b a n k n w r i t e - a p b a n k m w r i t e w i t h b u r s t o f 4 i n t e r r u p t b u r s t , p r e c h a r g e r e a d w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e r e a d - a p b a n k n d o u t a d o n t c a r e d q m d q c l = 3 ( b a n k n ) n o t e : d q m i s h i g h a t t 2 t o p r e v e n t d o u t a + 1 f r o m c o n t e n d i n g w i t h d i n d a t t 4 . d i n d d i n d + 1 d i n d + 2 d i n d + 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 20 - revision: a01 - 001 8.3.4 write with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a write on bank n when registered, with the data - out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data in registered one clock prior to the read to bank m. 8.3.5 write with auto precharge interrupted by a write (with or without auto precharge) a read to bank m will interrupt a write on bank n when registered, with the data - out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. th e last valid write to bank n will be data in registered one clock prior to the read to bank m. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p p r e c h a r g e d o u t d b a n k n , c o l a b a n k m , c o l d t r p - b a n k m t r p - b a n k n r e a d - a p b a n k m r e a d w i t h b u r s t o f 4 i n t e r r u p t b u r s t , w r i t e - b a c k w r i t e w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e w r i t e - a p b a n k n c l = 3 ( b a n k m ) d o n t c a r e n o t e : d q m i s l o w . t w r - b a n k n d i n a d i n a + 1 d o u t d + 1 c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p p r e c h a r g e b a n k n , c o l a b a n k m , c o l d t w r - b a n k m t r p - b a n k n w r i t e - a p b a n k m w r i t e w i t h b u r s t o f 4 i n t e r r u p t b u r s t , w r i t e - b a c k w r i t e w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e w r i t e - a p b a n k n d o n t c a r e n o t e : d q m i s l o w . t w r - b a n k n w r i t e - b a c k d i n a d i n a + 1 d i n a + 2 d i n d d i n d + 1 d i n d + 2 d i n d + 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 21 - revision: a01 - 001 8.4 burst termination the read or write command can be issued on any clock cycle. whenever a read operation is to be interrupted by a w rite command, the output data must be masked by dqm to avoid i/o conflict. also, when a write operation is to be interrupted by a read command, only the input data before the read command is enable and the input data afte r the read command is disabled. - r ead interrupted by a precharge a precharge command can be issued to terminate a burst cycle early. when a burst read cycle is interrupted by a precharge command, the read operation is terminated after ( cas latency - 1) clock cyc les from the precharge command. - w rite interrupted by a precharge a burst write cycle can be interrupted by a precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. in this case, the dqm signal must be asserted high to pr event writing the invalid data to the cell array. - r ead interrupted by a burst stop when the burst stop command is issued for the bank in a burst cycle, the burst operation is terminated. when the burst stop command is issued during a burst read cycle, th e read operation is terminated after clock cycle of ( cas latency - 1) from the burst stop command. - wr ite interrupted by a burst stop when the burst stop command is issued during a burst write cycle, the write operation is terminated at the same clock cycle that th e burst stop command is issued. - write interrupted by a read a burst of write operation can be interrupted by a read command. the read command interrupts the write operation on the same clock that the read command is issued. all the burst writes t hat are presented on the data bus before the read command is issued will be written to the memory. any remaining burst writes will be ignored once the read command is activated. there must be at least one clock bubble (hi - z state) on the da ta bus to avoid bus contention. - read interrupted by a write a burst of read operation can be interrupted by a write command by driving output drivers in a hi - z state using dqm before write to avoid data conflict. dqm should be utilized if there is data from a re a d comma nd on the first and second cycles of the subsequent write cycles to ensure the read data are tri - stated. from the third clock cycle, the write command will control the data bus and dqm is not needed .
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 22 - revision: a01 - 001 8.5 mode register operation the mode register designates t he operation mode for the read or write cycle. this register is divided into three fields; a burst length field to set the length of burst data, an addressing mode selected bits to designate the column access sequence in a burst cycle, and a cas latency fi eld to set the access time in clock cycle. the mode register is programmed by the mode register set command when all banks are in the idle state. the data to be set in the mode register is transferred using the a0~a n , ba0, ba1 address inputs. the initial v alue of the mode register after power - up is undefined; therefore the mode register set command must be issued before proper operation. 8.5.1 burst length field (a2~a0) this field specifies the data length for column access using the a2~a0 pins and sets the burst length to be 1, 2, 4, 8, words, or full - page. a 2 a1 a0 bust length 0 0 0 1 word 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 1 1 full - page 8.5.2 addressing mode select (a3) the addressing mode can be one of two modes; interleave mode or sequential mode. when the a3 bit is 0, sequential mode is selected. when the a3 bit is 1, interleave mode is selected. both addressing modes support burst length of 1, 2, 4 and 8 words. additionally, sequential mode supports the full - page burst. a3 addressing mode 0 sequ ential 1 interleave 8.5.3 addressing sequence for sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length shown as below table . d ata access address burst length data 0 n 2 words (address bit is a0) data 1 n + 1 not carr ied from a0 to a1 data 2 n + 2 4 words (address bit is a1, a0) data 3 n + 3 not carr ied from a1 to a2 data 4 n + 4 data 5 n + 5 8 words (address bit is a2, a1, a0) data 6 n + 6 not carr ied from a2 to a3 data 7 n + 7
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 23 - revision: a01 - 001 8.5.4 addressing sequence for interleave mode a column access is started from the input column address and is performed by inverting the address bits in the sequence shown as below table . d ata access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 data 2 a8 a7 a6 a5 a4 a3 a2 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 data 4 a8 a7 a6 a5 a4 a3 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a1 data 6 a8 a7 a6 a5 a4 a3 a0 data 7 a8 a7 a6 a5 a4 a3 8.5.5 addressing sequence example (burst length = 8 and input address is 13) data interleave mode sequential mode a8 a7 a6 a5 a4 a3 a2 a1 a0 add add calculated using a2, a1 and a0 bits not carry from a2 to a3 bit. data0 0 0 0 0 0 1 1 0 1 13 13 13 data1 0 0 0 0 0 1 1 0 0 12 13 + 1 14 data2 0 0 0 0 0 1 1 1 1 15 13 + 2 15 data3 0 0 0 0 0 1 1 1 0 14 13 + 3 8 data4 0 0 0 0 0 1 0 0 1 9 13 + 4 9 data5 0 0 0 0 0 1 0 0 0 8 13 + 5 10 data6 0 0 0 0 0 1 0 1 1 11 13 + 6 11 data7 0 0 0 0 0 1 0 1 0 10 13 + 7 12 8.5.6 read cycle cas latency = 3 a0 a1 a2 a2 r e a d 1 3 q 0 0 1 2 3 4 5 6 7 8 1 0 9 1 1 q 1 q 2 q 3 q 4 q 5 q 6 q 7 1 3 1 2 1 5 1 4 9 8 1 1 1 0 1 3 1 4 1 5 8 9 1 0 1 1 1 2 d a t a a d d r e s s { i n t e r l e a v e m o d e s e q u e n t i a l m o d e c o m m a n d a d d r e s s d q 0 ~ d q 7
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 24 - revision: a01 - 001 8.5.7 cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first data read. the minimum values of cas latency depends on the frequency of clk. the minimum value which satisfies the following formula must be set in this field . a6 a5 a4 cas latency 0 1 0 2 clock 0 1 1 3 clock ? reserved bits (a7, a8, a10, a11, a12, ba0, ba1) these bits are reserved for future operations. they must be set to 0 for normal operation. ? single write mode (a9) this bit is used to select the write mode. when the a9 bit is 0, burst read and burst write mode are selected. when the a9 bit is 1, burst read and single write mode are selected. a9 write mode 0 burst read and burst write 1 burst read and single write 8.5.8 mode register definition a 0 a 3 a d d r e s s i n g m o d e 0 s e q u e n t i a l 1 i n t e r l e a v e a 0 a 9 s i n g l e w r i t e m o d e 0 b u r s t r e a d a n d b u r s t w r i t e 1 b u r s t r e a d a n d s i n g l e w r i t e a 2 a 1 a 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 b u r s t l e n g t h s e q u e n t i a l i n t e r l e a v e 1 1 2 2 4 4 8 8 r e s e r v e d r e s e r v e d a 0 f u l l p a g e c a s l a t e n c y r e s e r v e d 2 3 r e s e r v e d a 6 a 5 a 4 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 r e s e r v e d a 0 a 1 a 2 a 3 a 4 a 5 a 6 b u r s t l e n g t h a d d r e s s i n g m o d e c a s l a t e n c y a 8 r e s e r v e d a 0 a 7 a 0 a 9 w r i t e m o d e a 1 0 a 1 1 b a 0 " 0 " " 0 " r e s e r v e d " 0 " " 0 " b a 1 " 0 " " 0 " " 0 " a 1 2 r e s e r v e d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 25 - revision: a01 - 001 8.6 extended mode register description the extended mode register designates the operation condition while sdram is in self refresh mode and selects the output driver strength as full, 1/2, 1/4, or 1/8 strength. the register is divided into t wo fields; (1) partial array self refresh field selects how much banks or which part of a bank need to be refreshed during self r efresh. (2) driver strength selected bit to control the size of output buffer. the initial value of the extended mode register after power - up is full driver strength, and all banks are refreshed during self refresh mode . e x t e n d e d m o d e r e g i s t e r s e t a 0 a 1 a 2 a 3 a 4 a 5 a 6 p a r t i a l a r r a y s e l f r e f r e s h a 8 a 7 a 9 a 1 0 a 1 1 b a 0 " 0 " " 0 " r e s e r v e d " 1 " b a 1 " 0 " " 0 " o u t p u t d r i v e r " 0 " " 0 " a 1 2 " 0 " " 0 " " 0 " r e s e r v e d a 2 a 1 a 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 r e s e r v e d s e l f - r e f r e s h c o v e r a g e a l l b a n k s r e s e r v e d r e s e r v e d a 6 a 5 d r i v e r s t r e n g t h f u l l s t r e n g t h 1 / 2 s t r e n g t h 0 0 0 1 1 0 1 1 1 / 4 s t r e n g t h 1 / 8 s t r e n g t h r e s e r v e d r e s e r v e d b a n k 0 ( b a 1 = b a 0 = 0 ) b a n k s 0 a n d 1 ( b a 1 = 0 )
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 26 - revision: a01 - 001 8.7 simplified state diagram m o d e r e g i s t e r s e t i d l e a u t o r e f r e s h s e l f r e f r e s h r o w a c t i v e p o w e r d o w n p r e c h a r g e p o w e r o n w r i t e w r i t e s u s p e n d w r i t e a w r i t e a s u s p e n d r e a d s u s p e n d r e a d r e a d a s u s p e n d r e a d a p r e m r s / e m r s a r e f a c t c s e c s e x c s e c s e x c s e c s e x s e l f s e l e x p d p d e x w r i t a r e a d w r i t r e a d a w r i t w r i t r e a d r e a d b s t b s t p r e c o m m a n d s e q u e n c e a u t o m a t i c s e q u e n c e d e e p p o w e r d o w n d p d d p d e x p r e p r e p o w e r d o w n p d p d e x r e a d a w r i t a c s e c s e x p o w e r a p p l i e d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 27 - revision: a01 - 001 9. electrical characteristics 9.1 a bsolute m aximum r atings parameter s ymbol values unit min max voltage on v dd relative to v ss v dd ? 0. 5 2. 3 v voltage on v ddq relative to v ss v ddq ? 0. 5 2. 3 v voltage on any pin relative to v ss v in , v out ? 0. 5 2. 3 v operating temperature t case - 25 85 c - 4 0 85 storage temperature t stg - 55 150 c short circuit output current i out 50 ma power dissipation p d 1.0 w note: stresses greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability 9.2 operating conditions parameter symbol min typ max unit supply voltage v dd 1.7 1.8 1.9 5 v supply voltage (for i/o buffer) v ddq 1. 7 1.8 1.9 5 v input high level voltage v ih 0.8 x v ddq - v ddq + 0.3 v input low level voltage v il - 0.3 - +0.3 v lv coms output ? h ? level voltage (i out = - 0.1 ma ) v oh 0.9 x v ddq - - v lv cmos output ? l ? level voltage (i out = +0.1 ma ) v ol - - 0.2 v input leakage current (0v v in v dd , all other pins not under test = 0v) i i(l) - 1 - 1 ? a output leakage current (output disable , 0v v out v ddq ) i o(l) - 5 - 5 ? a note : v ih (max) = v dd / v ddq +1. 2 v for pulse width 5 ns v il (min) = v ss / v ssq - 1. 2 v for pulse width 5 ns 9.3 capacitance p arameter s ym bol m in . m ax . u nit input capacitance ( a [ n: 0 ] , b a 0, b a 1, , , , , dqm, cke) c i 1.5 3. 0 pf input capacitance (clk) c clk 1.5 3.5 pf input/output capacitance c io 3.0 6.5 pf note : these parameters are periodically sampled and not 100% tested. cs ras cas we
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 28 - revision: a01 - 001 9.4 dc characteristics ( x16 , x32 ) parameter s ym . - 6 - 7 5 u nit n otes max. max. operating current: active mode; burst = 1; read or write; t rc = t rc ( min ) i dd1 38 35 ma 2, 3, 4 standby current: power - down mode; all banks idle; cke = low i dd 2p 0.3 0.3 ma 5 standby current: nonpower - down mode; all banks idle; cke = high i dd 2n 10 10 ma standby current: active mode; cke = low; = high; all banks active; no accesses in progress i dd3p 3 3 ma 3, 4, 6 standby current: active mode; cke = hig h; = high; all banks active after t rcd met; no accesses in progress i dd 3n 25 25 ma 3, 4, 6 operating current: burst mode; read or write; all banks active; half of dq toggling every cycle i dd 4 75 70 ma 2, 3, 4 auto refresh current: t rfc = t rfc ( min ) cke = high; = high i dd 5 75 75 ma 2, 3, 4, 6 deep power down mode i zz 10 10 a 5, 8 9.5 automatic temperature compensated self refresh current feature partial array self refresh setting emr [2:0] operating temperature setting emr[4:3] sym max. u nit emr[2:0]=000 , cke=0.2v all 4 banks are refreshed 85 c i dd6 450 a emr[2:0]=001 , cke=0.2v bank 0 and 1 are refreshed 85 c 350 emr[2:0]=010 , cke=0.2v only bank 0 is refreshed 85 c 300 notes: 1. a full initialization sequence is required before proper device operation is ensured. 2. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open . 3. the i dd current will increase or decrease proportionally according to the amount of fr equency alteration for the test condition. 4. ad dress transitions average one transition every 2 clocks. 5. measurement is taken 500m s after entering into this operating mode to provide tester measuring unit settling time . 6. other input signals can transition only one time for every 2 clocks and are otherwis e at valid vih or vil levels. 7. cke is high during the refresh command period t rfc ( min ) else cke is low . 8. typical values at 25c (not a maximum value). 9. enables on - die refresh and address counters. 10. values for i dd 6 85c full array and partial array are guaranteed for the entire temperature range. all other i dd 6 values are estimated. cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 29 - revision: a01 - 001 9.6 ac characteristics and operating condition 9.6.1 ac characteristics (notes: 5, 6 , 7 ) parameter sym. - 6 - 75 u nit n otes m in . m ax . m in . m ax . ref/active to ref/active command period t rc 60 67.5 ns 8 active to precharge command period t ras 42 100000 45 100000 ns 8 active to read/write command delay time t rcd 18 18 ns 8 read/write(a) to read/write(b) command period t ccd 1 1 t ck 8 precharge to active command period t rp 18 18 ns 8 active(a) to active(b) command period t rrd 2 2 t ck 8 write recovery time t wr 15 15 ns write - recovery time (last data to read) t ld r 1 1 t ck clk cycle time cl* = 3 t ck 6 1000 7.5 1000 ns cl* = 2 9.6 1000 9.6 1000 ns clk high level width t ch 2 .5 2 .5 ns clk low level width t cl 2 .5 2 .5 ns access time from clk cl* = 3 t ac 5 5.4 ns cl* = 2 6 8 ns output data hold time t oh 2.5 2.5 ns output data high impedance time cl* = 3 t hz 5 5.4 ns 7 cl* = 2 8 6 ns 7 output data low impedance time t lz 1. 0 1. 0 ns power down mode entry time t sb 0 6 0 7 .5 ns transition time of clk (rise and fall) t t 0.3 1 .2 0.3 1 .2 ns data - in set - up time t ds 1.5 1.5 ns data - in hold time t dh 1 1 ns address set - up time t as 1.5 1.5 ns address hold time t ah 1 1 ns cke set - up time t cks 1.5 1.5 ns cke hold time t ckh 1 1 ns command set - up time t cms 1.5 1.5 ns command hold time t cmh 1 1 ns refresh time t ref 64 64 ms mode register set cycle time t mrd 2 2 t ck 8 ref to ref/active command p eriod t rfc 7 2 7 2 ns self refresh e xit to n ext v alid c ommand d elay t xsr 120 1 15 ns * cl = cas latency
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 30 - revision: a01 - 001 9.6.2 ac test condition symbol parameter value unit v ih(min) input high voltage level (ac) 0.8 x v ddq v v il(max) input low voltage level (ac) 0.2 x v ddq v v otr outp ut signal reference level 0. 5 x v ddq v input signal transition time between v ih and v il is assumed as 1 volts/ns. notes: 1. conditions outside the limits listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect deice reliability . 2. all voltages are referenced to v ss and v ssq . 3. these parameters depend on the cycle rate. these values are measured at a cycle rate with the minimum values of t ck and t rc . input signals transition once per t ck period . 4. these parameters depend on the output loading. specified values are obtained with the output open . 5. power - up sequence is described in n ote 9 . 6. ac t est c onditions : (refer to 9 .6.2) . 7. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels . 8. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number) . 9. power up sequence : the sdram should be powered up by the following sequence of operations . a. power must be applied to v dd before or at the same time as v ddq while all input signals are held in the nop state. the clk signal will be applied at power up with power. b. after power - up a pause of at least 200 s is required. it is required that dqm and cke signals must be held high (v dd levels ) to ensure that the dq output is in high - impedance state. c. all banks must be precharged. d. the mode register set command must be issued to initialize the mode register. e. the extended mode register set command must be issued to initialize the extended mode register. f. issue two or more auto refresh dummy cycles to stabilize the internal circuitry of the device. the mode register set command can be invoked either before or after the auto refresh dummy cycles. t i m e r e f e r e n c e l o a d i / o z 0 = 5 0 o h m s 2 0 p f
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 31 - revision: a01 - 001 9.6.3 ac latency characteristics cke to clock disable (cke latency) 1 cycle dqm to output to hi - z (read dqm latency) 2 dqm to output to hi - z (write dqm latency) 0 write command to input data (write data latency) 0 to command input ( latency) 0 precharge to dq hi - z lead time cl = 2 2 cl = 3 3 precharge to last valid data out cl = 2 1 cl = 3 2 bust stop command to dq hi - z lead time cl = 2 2 cl = 3 3 bust stop command to last valid data out cl = 2 1 cl = 3 2 read with auto - precharge command to active/ref command cl = 2 bl + t rp cycle + ns cl = 3 bl + t rp write with auto - precharge command to active/ref command cl = 2 ( bl +1) + t rp cl = 3 ( bl +1) + t rp cs
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 32 - revision: a01 - 001 10. control t iming w aveform s 10.1 command input timing c l k a d d r e s s b a 0 , b a 1 v i h v i l t c m h t c m s t c h t c l t t t t t c k s t c k h t c k h t c k s t c k s t c k h c s r a s c a s w e c k e t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h t c k
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 33 - revision: a01 - 001 10.2 read timing r e a d c a s l a t e n c y t a c t l z t a c t o h t h z t o h b u r s t l e n g t h r e a d c o m m a n d c l k c s r a s c a s w e a d d r e s s b a 0 , b a 1 d q v a l i d d a t a - o u t v a l i d d a t a - o u t
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 34 - revision: a01 - 001 10.3 control timing of input data (x16) t c m h t c m s t c m h t c m s t d s t d h t d s t d h t d s t d h t d s t d h t c k h t c k s t c k h t c k s t d s t d h t d s t d h t d h t d s t d s t d h c l k l d q m d q 0 ~ d q 7 ( w o r d m a s k ) ( c l o c k m a s k ) c l k c k e d q 0 ~ d q 7 d q 8 ~ d q 1 5 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d h t d s t d s t d h d q 8 ~ d q 1 5 u d q m t c m h t c m s t c m h t c m s i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 35 - revision: a01 - 001 10.4 control timing of output data (x16) t c m h t c m s t c m h t c m s t o h t a c t o h t a c t o h t h z t l z t a c t o h t a c t c k h t c k s t c k h t c k s t o h t a c t o h t a c t o h t a c t o h t a c c l k ( o u t p u t e n a b l e ) ( c l o c k m a s k ) l d q m c k e c l k o p e n d q 0 ~ d q 7 d q 0 ~ d q 7 t c m h t c m s t c m h t c m s u d q m d q 8 ~ d q 1 5 o p e n t o h t a c t o h t a c t o h t a c t l z t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 8 ~ d q 1 5 t o h t h z o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 36 - revision: a01 - 001 10.5 control timing of input data (x32) t c m h t c m s t c m h t c m s t d s t d h t d s t d h t d s t d h t d s t d h t c k h t c k s t c k h t c k s t d s t d h t d s t d h t d h t d s t d s t d h c l k d q m 0 d q 0 ~ d q 7 ( w o r d m a s k ) ( c l o c k m a s k ) c l k c k e d q 0 ~ d q 7 d q 8 ~ d q 1 5 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d h t d s t d s t d h d q 8 ~ d q 1 5 d q m 1 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h * d q m 2 , 3 = l d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 t c m h t c m s t c m h t c m s * d q m 2 , 3 = l t d s t d h t d s t d h t d h t d s t d s t d h d q 1 6 ~ d q 2 3 t d s t d h t d s t d h t d h t d s t d s t d h d q 2 4 ~ d q 3 1 i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 37 - revision: a01 - 001 10.6 control timing of output data (x32) t c m h t c m s t c m h t c m s t o h t a c t o h t a c t o h t h z t l z t a c t o h t a c t c k h t c k s t c k h t c k s t o h t a c t o h t a c t o h t a c t o h t a c c l k ( o u t p u t e n a b l e ) ( c l o c k m a s k ) d q m 0 c k e c l k o p e n d q 0 ~ d q 7 d q 0 ~ d q 7 t c m h t c m s t c m h t c m s d q m 1 d q 8 ~ d q 1 5 t o h t a c t o h t a c t o h t a c t l z t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 8 ~ d q 1 5 d q m 2 , 3 = l t o h t a c t o h t a c t o h t a c t o h t h z t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 d q m 2 , 3 = l t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o p e n o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 38 - revision: a01 - 001 10.7 mode register set (mrs) cycle a 0 a 3 a d d r e s s i n g m o d e 0 s e q u e n t i a l 1 i n t e r l e a v e a 0 a 9 s i n g l e w r i t e m o d e 0 b u r s t r e a d a n d b u r s t w r i t e 1 b u r s t r e a d a n d s i n g l e w r i t e a 0 a 2 a 1 a 0 a 0 0 0 0 a 0 0 0 1 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 1 0 1 a 0 1 1 0 a 0 1 1 1 b u r s t l e n g t h s e q u e n t i a l i n t e r l e a v e 1 1 2 2 4 4 8 8 r e s e r v e d r e s e r v e d f u l l p a g e c a s l a t e n c y r e s e r v e d r e s e r v e d 2 3 r e s e r v e d a 0 a 6 a 5 a 4 a 0 0 0 0 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 0 0 1 * " r e s e r v e d " s h o u l d s t a y " 0 " d u r i n g m r s c y c l e . t r s c t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h c l k c s r a s c a s w e a d d r e s s b a 0 , b a 1 r e g i s t e r s e t d a t a n e x t c o m m a n d a 0 a 1 a 2 a 3 a 4 a 5 a 6 b u r s t l e n g t h a d d r e s s i n g m o d e c a s l a t e n c y ( t e s t m o d e ) a 8 a 0 a 7 a 9 a 0 w r i t e m o d e a 1 0 a n a 0 a 1 1 " 0 " " 0 " " 0 " " 0 " " 0 " r e s e r v e d b a 0 " 0 " r e s e r v e d b a 1 " 0 "
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 39 - revision: a01 - 001 10.8 extended mode register set (emrs) cycle * " r e s e r v e d " s h o u l d s t a y " 0 " d u r i n g e m r s c y c l e . t r s c t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h c l k c s r a s c a s w e a d d r e s s b a 0 , b a 1 r e g i s t e r s e t d a t a n e x t c o m m a n d a 0 a 1 a 2 a 3 a 4 a 5 a 6 p a s r a 8 a 1 0 b a 0 b a 1 a 2 a 1 a 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 p a r t i a l s e l f r e f r e s h a l l b a n k s r e s e r v e d e x t e n d e d m o d e r e g i s t e r s e t r e s e r v e d 0 0 0 1 0 a n o u t p u t d r i v e r 0 0 0 a 6 a 5 o u t p u t d r i v e r s t r e n g t h 0 0 f u l l s t r e n g t h 0 1 1 / 2 s t r e n g t h 1 0 1 1 1 / 4 s t r e n g t h 1 / 8 s t r e n g t h 0 0 r e s e r v e d b a n k 0 , 1 ( b a 1 = 0 ) b a n k 0 ( b a 0 = b a 1 = 0 ) a 9 a 1 1 a 7
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 40 - revision: a01 - 001 11. o perating t iming e xample 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 w e c s t r c t r c t r c t r c t r a s t r p t r a s t r p t r p t r a s t r a s t r c d t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d p r e c h a r g e p r e c h a r g e p r e c h a r g e r a a r b b r a c r b d r a e r a a c a w r b b c b x r a c c a y r b d c b z r a e a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 r a s c a s b a 1 b a 0 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 41 - revision: a01 - 001 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto - precharge) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s b a 0 t r c t r c t r c t r a s t r p t r a s t r p t r a s t r p t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d t r c r a a r a c r b d r a e d q a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 d z 0 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g a p * a p * r a a c a w r b b c b x r a c c a y r b d r a e c b z r b b a p * t r c d b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 t r a s
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 42 - revision: a01 - 001 11.3 interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 b y 0 b y 1 b y 4 b y 5 b y 6 b y 7 c z 0 c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s a c t i v e r e a d p r e c h a r g e a c t i v e r e a d p r e c h a r g e a c t i v e t a c t a c r e a d p r e c h a r g e t a c b a 0 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 43 - revision: a01 - 001 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto - precharge) a d d r e s s 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 4 b y 5 b y 6 c z 0 r a a r a a c a x r b b r b b c b y r a c r a c c a z * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g a c t i v e r e a d a c t i v e a c t i v e r e a d t a c t a c t a c c l k d q c k e d q m a 1 0 w e c a s r a s c s r e a d a p * a p * b a 1 b a 0 t r a s t r p b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 44 - revision: a01 - 001 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 w r i t e p r e c h a r g e a c t i v e a c t i v e w r i t e p r e c h a r g e a c t i v e w r i t e c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s i d l e b a n k # 0 b a n k # 1 b a n k # 2 b a n k # 3 b a 0 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 45 - revision: a01 - 001 11.6 interleaved bank write (burst length = 8, auto - precharge) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a b r a c a x 0 a x 1 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 c a z * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s a c t i v e w r i t e w r i t e a c t i v e b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p * a c t i v e w r i t e a p * b a 0
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 46 - revision: a01 - 001 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t c c d t c c d t c c d t r a s t r a s t r c d t r c d t r r d r a a r a a c a i r b b r b b c b x c a y c a m c b z a 0 a 1 a 2 a 3 b x 0 b x 1 a y 0 a y 1 a y 2 a m 0 a m 1 a m 2 b z 0 b z 1 b z 2 b z 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s a c t i v e r e a d a c t i v e r e a d r e a d r e a d r e a d p r e c h a r g e t a c t a c t a c t a c t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p * b a 0
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 47 - revision: a01 - 001 11.8 page mode read / write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r a s t r c d t w r r a a r a a c a x c a y a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a y 1 a y 0 a y 2 a y 4 a y 3 q q q q q q d d d d d c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s a c t i v e r e a d w r i t e p r e c h a r g e t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 b a 0
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 48 - revision: a01 - 001 11.9 auto - p recharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 w e c a s r a s c s b a 1 t r c t r a s t r p t r a s t r c d t r c d t a c t a c a c t i v e r e a d a p * a c t i v e r e a d a p * r a a r a b r a a c a w r a b c a x a w 0 a w 1 a w 2 a w 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a 0 b x 0 b x 2 b x 1 b x 3 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 49 - revision: a01 - 001 11.10 auto - precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 w e c a s r a s c s b a 1 t r c t r c t r p t r a s t r p r a a t r c d t r c d r a b r a c r a a r a b c a x r a c b x 0 b x 1 b x 2 b x 3 a c t i v e a c t i v e w r i t e a p * a c t i v e w r i t e a p * * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 t r a s b a 0 c a w a w 0 a w 1 a w 2 a w 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 50 - revision: a01 - 001 11.11 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 a l l b a n k s p r e c h a g e a u t o r e f r e s h a u t o r e f r e s h ( a r b i t r a r y c y c l e ) t r c t r p t r c c l k d q c k e d q m a d d r e s s a 1 0 w e c a s r a s c s b a 0 , b a 1
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 51 - revision: a01 - 001 11.12 self refresh cycle 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r p t c k s t s b t c k s a r b i t r a r y c y c l e t r f c d e v i c e d e s e l e c t ( d s l ) c y c l e s e l f r e f r e s h e x i t s e l f r e f r e s h e n t r y a l l b a n k p r e c h a r g e t c k s n o t e : t h e d e v i c e e x i t t h e s e l f r e f r e s h m o d e a s y n c h r o n o u s l y a t t h e r i s i n g e d g e o f t h e c k e s i g n a l . a f t e r c k e g o e s h i g h , t h e d e v i c e d e s e l e c t o r n o - o p e r a t i o n c o m m a n d m u s t b e r e g i s t e r e d a t t h e i m m e d i a t e l y f o l l o w i n g c l k r i s i n g e d g e , a n d c k e m u s t r e m a i n h i g h a t l e a s t f o r t c k s d e l a y i m m e d i a t e l y a f t e r e x i t t h e s e l f r e f r e s h m o d e . a b u s t o f 8 k a u t o r e f e e s h c y c l e w i t h i n 7 . 8 s b e f o r e e n t e r i n g a n d e x i t i n g i s n e c e s s a r y i f t h e s y s t e m d o e s n o t u s e t h e a u t o r e f r e s h f u n c t i o n . c l k d q c k e d q m a d d r e s s a 1 0 b a 0 , b a 1 w e c a s r a s c s
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 52 - revision: a01 - 001 11.13 burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c s r a s c a s w e b a 1 b a 0 a 1 0 a d d r e s s d q m c k e d q t r c d r b a r b a c b v c b w c b x c b y c b z a v 0 a v 1 a v 2 a v 3 a w 0 a x 0 a y 0 a z 0 a z 1 a z 2 a z 3 q q q q d d d q q q q t a c t a c r e a d r e a d s i n g l e w r i t e a c t i v e b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 53 - revision: a01 - 001 11.14 power down mode 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 r a a c a a r a a c a x r a a r a a a x 0 a x 1 a x 2 a x 3 t s b t c k s t c k s t c k s t s b t c k s a c t i v e p o w e r d o w n m o d e e x i t p r e c h a r g e & p o w e r d o w n m o d e e n t r y d e v i c e d e s e l e c t a c t i v e n o t e : t h e p o w e r d o w n m o d e i s e n t e r e d b y a s s e r t i n g c k e " l o w " . a l l i n p u t / o u t p u t b u f f e r s ( e x c e p t c k e b u f f e r s ) a r e t u r n e d o f f i n t h e p o w e r d o w n m o d e . w h e n c k e g o e s h i g h , c o m m a n d i n p u t m u s t b e n o o p e r a t i o n a t n e x t c l k r i s i n g e d g e . v i o l a t i n g r e f r e s h r e q u i r e m e n t s d u r i n g p o w e r - d o w n m a y r e s u l t i n a l o s s o f d a t a . c l k d q c k e d q m a d d r e s s a 1 0 b a w e c a s r a s c s d s l p o w e r d o w n m o d e e x i t p o w e r d o w n m o d e e n t r y
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 54 - revision: a01 - 001 11.15 deep power down mode entry 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t s b t c k s a c t i v e b a n k s p r e c h a r g e c l k d q c k e d q m a d d r e s s a 1 0 b a 0 , b a 1 w e c a s r a s c s d e e p p o w e r d o w n e n t r y t r p
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 55 - revision: a01 - 001 11.16 deep power down mode exit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t c k s a l l b a n k s p r e c h a r g e c l k d q c k e d q m a 1 0 a d d r e s s w e c a s r a s c s d e e p p o w e r d o w n e x i t t r p t m r d t m r d o p - c o d e o p - c o d e d s l 2 0 0 s m o d e r e g i s t e r s e t e x t e n d e d m o d e r e g i s t e r s e t a u t o r e f r e s h a u t o r e f r e s h i s s u e a u t o r e f r e s h c y c l e t w o o r m o r e a r b i t r a r y c y c l e n o t e : t h e d e v i c e e x i t s t h e d e e p p o w e r d o w n m o d e a s y n c h r o n o u s l y a t t h e r i s i n g e d g e o f t h e c k e s i g n a l . a f t e r c k e g o e s h i g h , t h e d e v i c e d e s e l e c t o r n o - o p e r a t i o n c o m m a n d m u s t b e r e g i s t e r a t t h e i m m e d i a t e l y f o l l o w i n g c l k r i s i n g e d g e , a n d c k e m u s t r e m a i n h i g h a t l e a s t f o r t c k s d e l a y i m m e d i a t e l y a f t e r e x i t i n g t h e d e e p p o w e r d o w n m o d e . t r f c t r f c
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 56 - revision: a01 - 001 11.17 auto - precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period f rom bank activ ate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activ ate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 57 - revision: a01 - 001 11.18 auto - precharge timing (write cycle) 0 1 3 2 ( 1 ) b u r s t l e n g t h = 1 d q 4 5 7 6 8 9 1 1 1 0 w r i t e d 0 a c t a p c o m m a n d ( 2 ) b u r s t l e n g t h = 2 d q w r i t e d 0 a c t a p c o m m a n d t r p t r p d 1 ( 3 ) b u r s t l e n g t h = 4 d q d 0 a c t a p c o m m a n d t r p d 1 ( 4 ) b u r s t l e n g t h = 8 d q w r i t e / a d 0 a c t a p c o m m a n d t r p d 1 d 2 d 3 d 2 d 3 d 4 d 5 d 6 d 7 1 2 w r i t e a c t a p w h e n t h e a u t o p r e c h a r g e c o m m a n d i s a s s e r t e d , t h e p e r i o d f r o m b a n k a c t i v a t e c o m m a n d t o t h e s t a r t o f i n t e r n a l p r e c g a r g i n g m u s t b e a t l e a s t t r a s ( m i n ) . n o t e : r e p r e s e n t s t h e b a n k a c t i v a t e c o m m a n d . r e p r e s e n t s t h e s t a r t o f i n t e r n a l p r e c h a r g i n g . r e p r e s e n t s t h e w r i t e w i t h a u t o p r e c h a r g e c o m m a n d . w r i t e / a r e p r e s e n t s t h e w r i t e c o m m a n d . r e p r e s e n t s t h e p r e c h a r g e c o m m a n d . w r i t e p r e t w r t w r w r i t e / a w r i t e p r e t w r t w r w r i t e / a p r e t w r t w r w r i t e / a t w r t w r p r e 1 . 2 . 3 . f o r w r i t e w i t h o u t a u t o - p r e c h a r g e , t w r = 1 5 n s . f o r w r i t e w i t h a u t o - p r e c h a r g e , t w r = 2 t c k . 4 . p r e
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 58 - revision: a01 - 001 11.19 timing chart of read to write cycle 11.20 timing chart of write to read cycle note: the output data must be masked by dqm to avoid i/o conflict. read write 11 10 9 8 7 6 5 4 3 2 1 read read read write write d0 d1 d2 d3 write dq dq ( a ) command 0 dq dq dqm ( b ) command dqm ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 (1) cas latency=2 ( a ) command (2) cas latency=3 in the case of burst length = 4 1 0 ( 1 ) c a s l a t e n c y = 2 ( a ) c o m m a n d d q d q ( 2 ) c a s l a t e n c y = 3 i n t h e c a s e o f b u r s t l e n g t h = 4 d q m ( b ) c o m m a n d d q m t l d r t l d r w r i t e r e a d 0 1 2 3 4 5 6 7 8 9 1 1 d o q o q 1 q 2 q 3 w r i t e r e a d d o d 1 q o q 1 q 2 q 3 ( a ) c o m m a n d d q d q d q m ( b ) c o m m a n d d q m t l d r t l d r w r i t e r e a d d o q o q 1 q 2 q 3 w r i t e r e a d d o d 1 q o q 1 q 2 q 3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 59 - revision: a01 - 001 11.21 timing chart of burst stop cycle (burst stop command) 11.22 timing chart of burst stop cycle (precharge command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 c omma nd ( b )cas latency = 3 (1) read cycle q4 (2) write cycle c omma nd read c omma nd q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 0 1 1 1 1 0 9 8 7 6 5 4 3 2 ( 1 ) r e a d c y c l e ( a ) c a s l a t e n c y = 2 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g r e a d ( b ) c a s l a t e n c y = 3 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g r e a d d q d q ( 2 ) w r i t e c y c l e ( a ) c a s l a t e n c y = 2 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g w r i t e ( b ) c a s l a t e n c y = 3 c o m m a n d q 0 q 1 q 2 q 3 q 4 w r i t e d q d q d q m d q m p r c g t w r t w r n o t e : r e p r e s e n t s t h e p r e c h a r g e c o m m a n d . p r c g i n t h e c a s e o f b u r s t l e n g t h = 8 w r i t e d q m l a t e n c y = 0 w r i t e d q m l a t e n c y = 0
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 60 - revision: a01 - 001 11.23 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 61 - revision: a01 - 001 11.24 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk q3
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 62 - revision: a01 - 001 12. p ackage s pecification 12.1 lpsdr x16 package outline v f bga 54 balls ( 8 x 9 mm 2 , ball pitch:0. 8 mm, ? =0.4 5 mm) b a l l l a n d b a l l o p e n i n g n o t e : 1 . b a l l l a n d : 0 . 5 m m 2 . b a l l o p e n i n g : 0 . 4 m m 3 . p c b b a l l l a n d s u g g e s t e d 0 . 4 m m b e j h g f e d c b d 1 1 2 3 4 5 6 7 8 9 e 1 p i n # 1 a C a C d a a a C b C a a a e s o l d e r b a l l s e a t i n g p l a n e c a v i t y c b b b / / C c C c c c c a 2 a 1 a s y m b o l d i m e n s i o n i n m m d i m e n s i o n i n i n c h m i n n o m m a x m i n n o m m a x a d e e b a a a b b b c c c d 1 e 1 a 1 a 2 0 . 2 7 5 0 . 3 0 0 0 . 3 2 5 0 . 6 1 0 . 6 6 0 . 7 1 7 . 9 0 8 . 0 0 8 . 1 0 8 . 9 0 9 . 0 0 9 . 1 0 0 . 4 0 0 . 4 5 0 . 5 0 1 . 0 2 5 - - - - - - 0 . 0 4 0 - - - - - - 0 . 0 1 1 0 . 0 1 2 0 . 0 1 3 0 . 0 2 4 0 . 0 2 6 0 . 0 2 8 0 . 3 1 1 0 . 3 1 5 0 . 3 1 9 0 . 3 5 0 0 . 3 5 4 0 . 3 5 8 0 . 0 1 6 0 . 0 1 8 0 . 0 2 0 0 . 8 0 - - - - - - 6 . 4 0 - - - - - - 6 . 4 0 - - - - - - 0 . 2 5 2 - - - - - - 0 . 2 5 2 - - - - - - 0 . 0 3 1 - - - - - - 0 . 1 5 0 . 2 0 0 . 1 2 0 . 0 0 6 0 . 0 0 8 0 . 0 0 5 n o t e : d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d .
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 63 - revision: a01 - 001 12.2 lpsdr x 32 package outline vf bga 90 balls ( 8 x 13 mm 2 , ball pitch:0. 8 mm, ? =0.4 5 mm) b a l l l a n d b a l l o p e n i n g n o t e : 1 . b a l l l a n d : 0 . 5 m m 2 . b a l l o p e n i n g : 0 . 4 m m 3 . p c b b a l l l a n d s u g g e s t e d 0 . 4 m m b e r p h g f e d c b d 1 1 2 3 4 5 6 7 8 9 e 1 p i n # 1 a C a C d a a a C b C a a a e s o l d e r b a l l s e a t i n g p l a n e c a v i t y c b b b / / C c C c c c c a 2 a 1 a s y m b o l d i m e n s i o n i n m m d i m e n s i o n i n i n c h m i n n o m m a x m i n n o m m a x a d e e b a a a b b b c c c d 1 e 1 a 1 a 2 0 . 2 7 5 0 . 3 0 0 0 . 3 2 5 0 . 6 1 0 . 6 6 0 . 7 1 7 . 9 0 8 . 0 0 8 . 1 0 1 2 . 9 0 1 3 . 0 0 1 3 . 1 0 0 . 4 0 0 . 4 5 0 . 5 0 1 . 0 2 5 - - - - - - 0 . 0 4 0 - - - - - - 0 . 0 1 1 0 . 0 1 2 0 . 0 1 3 0 . 0 2 4 0 . 0 2 6 0 . 0 2 8 0 . 3 1 1 0 . 3 1 5 0 . 3 1 9 0 . 5 0 8 0 . 5 1 2 0 . 5 1 6 0 . 0 1 6 0 . 0 1 8 0 . 0 2 0 0 . 8 0 - - - - - - 1 1 . 2 0 - - - - - - 6 . 4 0 - - - - - - 0 . 2 5 2 - - - - - - 0 . 4 4 1 - - - - - - 0 . 0 3 1 - - - - - - 0 . 1 5 0 . 2 0 0 . 1 2 0 . 0 0 6 0 . 0 0 8 0 . 0 0 5 n m l k j n o t e : d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d .
w989 d 6db / w989d2db publication release date: mar. 1 9 , 2014 - 64 - revision: a01 - 001 13. revision history version date page description a 0 1 - 00 1 mar. 1 9 , 2014 all initial formally data shee t important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbon d customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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